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PD-97051A
iP2003APbF
Synchronous Buck Multiphase Optimized LGA Power Block
Features:

Integrated Power Semiconductors, Drivers & Passives
Full function multiphase building block Output current 40A continuous with no derating up to TPCB = 100C and TCASE = 100C Operating frequency up to 1.0 MHz Proprietary packaging enables ultra low Rthj-case top Efficient dual sided cooling Small footprint low profile (9mm x11mm x 2.2mm) package Optimized for very low power losses LGA interface Ease of design
iP2003APbF Power Block
Description The iP2003APbF is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm power block. The only additional components required for a complete multiphase converter are a PWM controller, the output inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection.
Pin #
1
iP2003APbF Internal Block Diagram
VSWS1 VSWS2
Pin N am e Pin Function V DD Supply voltage for the internal circuitry.
2
ENA BLE
W hen set to logic level high, internal circuitry of the device is enabled. W hen set to logic level low, the PRD Y pin is forced low, the Control and Sychronous switches are turned off, and the supply current reduces to 10 A. T T L-level input signal to M OSFET drivers. Power Ready - This pin indicates the status of EN AB LE or V D D . T his output will be driven low when EN ABLE is logic low or when V D D is less than 4.4V (typ.). W hen EN AB LE is logic high and V D D is greater than 4.4V (typ.), this output is driven high. T his output has a 10mA source and 1mA sink capability. Power G round - connection to the ground of bulk and filter capacitors. Switching N ode - connection to the output inductor. Input voltage pin. External bypass ceramic capacitors must be added directly next to the block. Floating pin. For internal use. E xternally, short to V SW S2 pin only . Floating pin. For internal use. E xternally, short to V SW S1 pin only .
VIN PRDY ENABLE PWM VDD MOSFET Driver with dead time control
3
PW M
VSW
4
PRD Y
PGND
5, 7 6
PG ND V SW V IN V SW S1 V SW S2
PACKAGE DESCRIPTION
INTERFACE CONNECTION
PARTS PER BAG
PARTS PER REEL
T&R ORIENTATION
8 9
iP2003APbF IP2003ATRPBF
LGA LGA
10 ---
--1000
Fig 12
10
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8/16/06
1
iP2003APbF
VDD to PGND PWM to PGND Enable to PGND Output RMS Current
All specifications @25C (unless otherwise specified)
Min -0.3 -0.3 Typ Max 16 6.0 VDD +0.3 VDD +0.3 40 Units V V V V A Not to exceed 6.0V Not to exceed 6.0V Measured at VSW Conditions
Absolute Maximum Ratings: Parameter Symbol VIN to PGND VIN VDD PWM ENABLE IOUT
Recommended Operating Conditions: Min Parameter Symbol
Supply Voltage Input Voltage Output Voltage Output Current Operating Frequency Operating Duty Cycle Block Temperature VDD VIN VOUT IOUT fsw D TBLK 4.6 3.0 0.8 300 -40
Typ
5.0 -
Max
5.5 13.2 3.3 40 1000 85 125
Units
V V V A kHz % C
Conditions
Electrical Specifications @ VDD = 5V (unless otherwise specified): Parameter Symbol Min Typ Max Units PLOSS Block Power Loss c 9.4 11.7 W Turn On Delay d Turn Off Delay d VIN Quiescent Current VDD Quiescent Current Under-Voltage Lockout Start Threshold Hysteresis Enable Input Voltage High Input Voltage Low Power Ready Logic Level High Logic Level Low PWM Input Logic Level High Logic Level Low td(on) td(off) IQ-VIN IQ-VDD UVLO VSTART VHvs-UVLO ENABLE VIH VIL PRDY VOH VOL PWM VOH VOL 4.2 2.1 4.5 2.1 63 26 10 4.4 150 4.6 0.1 1.0 4.5 0.8 0.2 0.8 V V ns mA A V mV V
Conditions
VIN=12V, VOUT=1.3V IOUT=40A, fSW=1MHz L = 0.3H Enable = 0V, VIN=12V Enable = 0V, VDD=5V
VDD=4.6V, ILoad=10mA VDD Measurement made using six 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see 2
Fig. 8). Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
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iP2003APbF
16 14 12
Power Loss (W)
VIN = 12V VOUT = 1.3V f sw L = 1MHz = 0.30H T BLK = 125C
10 8 6 4 2 0 0 5 10 15 20 Output Current (A)
Maximum Typical
25
30
35
40
Fig. 1: Power Loss vs. Current
Case Temperature (C)
0
40 36 32
Output Current (A)
10
20
30
40
50
60
70
80
90
100
110
120
130
28 24 20 16 12 8 4 0 0 10 20 30 VIN = 12V VOUT = 1.3V f sw L = 1MHz = 0.30H
Safe Operating Area
Tx
40
50
60
70
80
90
100
110
120
130
PCB Temperature (C)
Fig. 2: Safe Operating Area (SOA) vs. TPCB & TCASE www.irf.com 3
iP2003APbF
Typical Performance Curves
1.28 1.24
Power Loss (Normalized)
Power Loss (Normalized)
VOUT = 1.3V I OUT = 40A f sw = 1MHz L = 0.3H T BLK = 125C
7 6 5 4 3 2 1 0 -1
SOA Temp Adjustment (C)
1.16 1.12 1.08 1.04 1.00 0.96 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 Output Voltage (V) VIN = 12V I OUT = 40A f sw = 1MHz L = 0.30H T BLK = 125C
4.0
SOA Temp Adjustment (C)
1.20 1.16 1.12 1.08 1.04 1.00 0.96 3 4 5 6 7 8 9
3.0
2.0
1.0
0.0
-1.0
10
11
12
13
Input Voltage (V)
Fig. 3: Normalized Power Loss vs. VIN
1.05
Power Loss (Normalized)
Fig. 4: Normalized Power Loss vs. VOUT
1
Power Loss (Normalized)
1.06
SOA Temp Adjustment (C)
1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 200
VIN = 12V VOUT = 1.3V IOUT = 40A L = 0.30H TBLK = 125C
0 -1 -2 -3 -4 -5 -6 -7
1.04
VIN = 12V VOUT = 1.3V I OUT = 40A f sw = 1MHz T BLK = 125C
1.5
SOA Temp Adjustment (C)
1.0
1.02
0.5
1.00
0.0
0.98 0.1 0.3 0.5 0.7 0.9 Output Inductance (H)
-0.5
300
400
500
600
700
800
900 1000
Switching Frequency (kHz)
Fig. 5: Normalized Power Loss vs. Frequency
100 90 Average IDD (mA) 80 70 60 50 40 300 400 500 600 700
Fig. 6: Normalized Power Loss vs. Inductance
Does not include PRDY current TBLK = 25C 800 900 1000
Switching Frequency (kHz)
4
Fig. 7: IDD (VDD current) vs. Frequency
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iP2003APbF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case.
Procedure
1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis. The point at which the horizontal line meets the Y-axis is the SOA current.
Output Current (A)
Case Temperature (C)
0 10 20 30 40 50 60 70 80 90 100 110 120
42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120
TX
Safe Operating Area
VIN = 12V VOUT = 1.3V fSW = 1MHz L=0.3uH
PCB Temperature (C)
Calculating Power Loss and SOA for Different Operating Conditions
To calculate power loss for a given set of operating conditions, the following procedure should be followed: Determine the maximum current for each iP2003APbF and obtain the maximum power loss from Fig 1. Use the curves in Figs. 3, 4, 5 and 6 to obtain normalized power loss values that match the operating conditions in the application. The maximum power loss under the operating conditions is then the product of the power loss from Fig. 1 and the normalized values. To calculate the SOA for a given set of operating conditions, the following procedure should be followed: Determine the maximum PCB temperature and Case temperature at the maximum operating current of each iP2003APbF. Obtain the SOA temperature adjustments that match the operating conditions in the application from Figs. 3, 4, 5 and 6. Then, add the sum of the SOA temperature adjustments to the Tx axis intercept in Fig 2. The example below explains how to calculate maximum power loss and SOA. Example: Operating Conditions Output Current = 40A Sw Freq= 900kHz Calculating Maximum Power Loss: (Fig. 1) (Fig. 3) (Fig. 4) (Fig. 5) (Fig. 6) Maximum power loss = 15W Normalized power loss for input voltage 0.98 Normalized power loss for output voltage 1.14 Normalized power loss for frequency 0.94 Normalized power loss for inductor value 1.013 Input Voltage = 10V Inductor = 0.2H Output Voltage = 3.3V TPCB = 100C, TCASE = 110C
Calculated Maximum Power Loss for given conditions = 15W x 0.98 x 1.14 x 0.94 x 1.013 15.96W
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5
iP2003APbF
Calculating SOA Temperature: (Fig. (Fig. (Fig. (Fig. 3) 4) 5) 6) SOA Temperature Adjustment SOA Temperature Adjustment SOA Temperature Adjustment SOA Temperature Adjustment for for for for input voltage -0.5C output voltage 3.3C frequency -1.2C inductor value 0.25C
TX axis intercept temp adjustment = - 0.5C + 3.3C - 1.2C + 0.25C 1.85C Assuming TCASE = 110C & TPCB = 100C: The following example shows how the SOA current is adjusted for a TX increase of 1.85C.
Case Temperature (C)
0 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120
Output Current (A)
TX Safe Operating Area
VIN = 12V VOUT = 1.3V fSW = 1MHz L=0.3uH
10 20 30 40 50
60
70
80
90
100
110
120
PCB Temperature (C)
PIN = V IN Average x IIN Average PDD = V DD Average x IDD Average POU T = VOUT Average x IOU T Average PLOSS = (PIN + PDD ) - POUT
Average Input Current (IIN ) A
DC
90%
V
Average Input Voltage (VIN )
PWM
10%
Average VDD Current (IDD ) A V
DC
PRDY ENABLE PWM VDD
VIN
Average Output Current (I ) OUT A
VSW
90%
Average VDD Voltage (VDD )
PGND
iP2003APbF iP2003A
VSW
Averaging Circuit V Average Output Voltage (VOUT )
10%
td(on)
td(off)
Fig. 8: Power Loss Test Circuit 6
Fig. 9: Timing Diagram www.irf.com
iP2003APbF
PCB Layout Guidelines
One of the most critical elements of proper PCB layout with iP2003APbF is the placement of the external input bypass capacitors and the routing of the connecting power tracks. It is recommended that the designer uses the following guidelines: 1. The diagram below suggests the addition of the input bypass capacitors either on the top side of the PCB (capacitors C1-C6) or top and bottom side (C7, C8), if placement on the bottom side is feasible. The amount of the input capacitors is based on the input ripple current handling requirement of the iP2003APbF. To support 12A input RMS current, based on 12V input, 1.3V and 40A output and 1MHz, the iP2003APbF will require enough input ceramic capacitors to support the input RMS AC current. These capacitors must be placed as close to the iPOWIR device as possible. In the diagram below, observe the routing of the power tracks that connect the external bypass capacitors. Provide a mid-layer solid ground plane with connections to the top through vias. Refer to IR application note AN-1029a to determine the size of the vias and the copper weight and thickness when designing the PCB.
2. 3. 4.
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7
iP2003APbF
2.5 [0.10]
2.0 [0.08]
0508 6B7D iP2003A iP2003AP
XX
Fig 10: Maximum TCASE measurement location
3.9116
2X
6
9.00 [.354]
B
A 0.332
8.509
0.15 [.006] C
1.9050
0.3556
0 0 1.2337 1.3593 2.2243 4.5183 6.9567 8.6124 8.9248
ORIENTATION CORNER ID 11.00 [.433]
VIN 3.253
VSWS1
VSWS2 VDD
PGND PGND
7.1773 VSW
ENABLE
PWM PRDY
T OP VIEW
0.15 [.006] C 2X 6
C S IDE VIEW
2.31 [.0909] 2.13 [.0839] 5
BOTTOM VIEW
(1) (2),(3) (4) (5)
X Y X Y X Y X Y
1.1430 2.1016 1.1430 1.1016 1.1430 1.2192 1.778 5.334
(6) (7) (8) (9),(10)
X Y X Y X Y X Y
3.429 3.429 3.429 3.048 4.953 2.032 1.016 0.635
NOTES : 1. 2. 3. 4. 5 6 DIMENS IONING & TOLERANCING PER AS ME Y14.5M-1994. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. CONTROLLING DIMENS ION: MILLIMETER LAND DES IGNAT ION PER JES D MO 222, S PP-010. PRIMARY DATUM C IS S EATING PLANE. BILATERAL TOLERANCE Z ONE IS APPLIED TO EACH S IDE OF T HE PACKAGE BODY.
LAYOUT NOTES : 1. LAND PATT ERN ON US ER' PCB S HOULD BE AN IDENTICAL MIRROR S IMAGE OF T HE PATTERN S HOWN IN THE BOT TOM VIEW. 2. LANDS S HOULD BE S OLDER MAS K DEFINED.
8
Fig 11: Mechanical Drawing
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iP2003APbF
Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products:
AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1047: Graphical solution for two branch heatsinking Safe Operating Area Detailed explanation of the dual axis SOA graph and how it is derived. AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers BGA and LGA Packages This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations . Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as soldering, pick and place, reflow, cleaning and reworking recommendations. AN-1029a: Optimizing a PCB Layout for an iPowir Technology Design IRDCiP2003A : Reference design for iP2003APbF
0508 6B7D iP2003A iP2003AP
XX
0508 6B7D iP2003A iP2003AP
24mm
XX
12mm NOTES :
FEED DIRECTION
1. OUT LINE CONFORMS T O EIA-481 & EIA-541.
iP2003APbF, LGA iP2003A, LGA
Fig. 12: Tape & Reel Information
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iP2003APbF
XX
Fig. 13: Part Marking
0.9906 1.9492 0.9906 0.9492 0.9906 1.0668 1.6764 5.2324
X Y X Y X Y X Y
A
I A J H
X Y X Y X Y X Y
F G H I,J
3.3274 3.3274 3.3274 2.9464 4.8514 1.9304 0.9144 0.5334
B,C
G E
B
D E
C D F
NOT ES : 1. T HIS VIEW IS S T ENCIL S QUEEGEE VIEW 2. DIMENS IONS ARE S HOWN IN MILLIMET ERS . 3. T HIS OPENING IS BAS ED ON US ING 150 MICRON S T ENCIL. IF US ING DIFFERENT T HICKNES S S TENCIL, T HIS OPENING NEEDS T O BE ADJUS T ED ACCORDINGLY
S T ENCIL DES IGN
The recommended reflow peak temperature not to exceed 260C. The total furnance time is approximately 5 minutes with approximately 10 seconds at the peak temperature.
Fig.14: Recommended solder profile and stencil design
Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.08/06 10 www.irf.com

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